VLSI development of smart-pixel ICs: A hybrid DSP core and a multi-threaded programmable DSP

J. Ekman, P. Chandramani, P. Rozier, F. Kiamilev, J. Rorie, F. Zane, P. Marchand, S. Esener

Research output: Contribution to journalConference article

Abstract

Two integrated circuits which target the development of digital integrated circuits with the capability to interface with optical devices to yield high-speed/high-bandwidth communication are presented. The first, fabricated with Hewlett-Packard's 14B half-micron process as a part of the 1997 Bell Labs/Lucent Technology CMOS-multiple quantum well (MQW) foundry, is a digital signal processing (DSP) core. The second is a prototype design of the multi-threaded programmable DSP engine that will be a part of the 3-D OESP consortium demonstrator system.

Original languageEnglish (US)
Pages (from-to)59-60
Number of pages2
JournalLEOS Summer Topical Meeting
StatePublished - Jan 1 1998
Externally publishedYes
EventProceedings of the 1998 IEEE/LEOS Summer Topical Meeting - Monterey, CA, USA
Duration: Jul 20 1998Jul 24 1998

ASJC Scopus subject areas

  • Atomic and Molecular Physics, and Optics
  • Electrical and Electronic Engineering

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    Ekman, J., Chandramani, P., Rozier, P., Kiamilev, F., Rorie, J., Zane, F., Marchand, P., & Esener, S. (1998). VLSI development of smart-pixel ICs: A hybrid DSP core and a multi-threaded programmable DSP. LEOS Summer Topical Meeting, 59-60.