Abstract
We report about ongoing work on a free-space optical interconnect system, which will demonstrate a Fast Fourier Transformation (FFT) calculation, distributed among six processor chips. Logically, the processors are arranged in two linear chains, where each element communicates optically with its nearest neighbors. Physically, the setup consists of a large motherboard, several multi-chip carrier modules, which hold the processor/driver chips and the optoelectronic chips (arrays of lasers and detectors), and several plug-on-top optics modules, which provide the optical links between the chip carrier modules. The system design tries to satisfy numerous constraints, such as compact size, potential for mass-production, suitability for large arrays (up to 1024 parallel channels), compatibility with standard electronics fabrication and packaging technology, potential for active misalignment compensation by integrating MEMS technology, and suitability for testing different imaging topologies. We present the system architecture together with details of key components and modules, and report on first experiences with prototype modules of the setup.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1037-1045 |
| Number of pages | 9 |
| Journal | Unknown Journal |
| Volume | 4089 |
| State | Published - 2000 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Condensed Matter Physics
Cite this
Parallel distributed free-space optoelectronic compute engine using flat `plug-on-top' optics package. / Berger, C.; Ekman, J.; Wang, X.; Marchand, P.; Spaanenburg, H.; Kiamilev, F.; Esener, Sadik.
In: Unknown Journal, Vol. 4089, 2000, p. 1037-1045.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Parallel distributed free-space optoelectronic compute engine using flat `plug-on-top' optics package
AU - Berger, C.
AU - Ekman, J.
AU - Wang, X.
AU - Marchand, P.
AU - Spaanenburg, H.
AU - Kiamilev, F.
AU - Esener, Sadik
PY - 2000
Y1 - 2000
N2 - We report about ongoing work on a free-space optical interconnect system, which will demonstrate a Fast Fourier Transformation (FFT) calculation, distributed among six processor chips. Logically, the processors are arranged in two linear chains, where each element communicates optically with its nearest neighbors. Physically, the setup consists of a large motherboard, several multi-chip carrier modules, which hold the processor/driver chips and the optoelectronic chips (arrays of lasers and detectors), and several plug-on-top optics modules, which provide the optical links between the chip carrier modules. The system design tries to satisfy numerous constraints, such as compact size, potential for mass-production, suitability for large arrays (up to 1024 parallel channels), compatibility with standard electronics fabrication and packaging technology, potential for active misalignment compensation by integrating MEMS technology, and suitability for testing different imaging topologies. We present the system architecture together with details of key components and modules, and report on first experiences with prototype modules of the setup.
AB - We report about ongoing work on a free-space optical interconnect system, which will demonstrate a Fast Fourier Transformation (FFT) calculation, distributed among six processor chips. Logically, the processors are arranged in two linear chains, where each element communicates optically with its nearest neighbors. Physically, the setup consists of a large motherboard, several multi-chip carrier modules, which hold the processor/driver chips and the optoelectronic chips (arrays of lasers and detectors), and several plug-on-top optics modules, which provide the optical links between the chip carrier modules. The system design tries to satisfy numerous constraints, such as compact size, potential for mass-production, suitability for large arrays (up to 1024 parallel channels), compatibility with standard electronics fabrication and packaging technology, potential for active misalignment compensation by integrating MEMS technology, and suitability for testing different imaging topologies. We present the system architecture together with details of key components and modules, and report on first experiences with prototype modules of the setup.
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M3 - Article
AN - SCOPUS:0033692149
VL - 4089
SP - 1037
EP - 1045
JO - Indian Journal of Rheumatology
JF - Indian Journal of Rheumatology
SN - 0973-3698
ER -