Optimization of transmitter and receiver design for optoelectronic computing

This report discusses the recent results in the design optimization of the overall photonics layer. The total electrical power dissipated in both the transmitter and the receiver modules is examined, and the receiver configurations are optimized to achieve a minimum electrical power dissipation at a given bit rate. The results indicate that, as the bit rate increases, the total power dissipation in the photonics layer increases while the interconnect channel density decreases. The actual physical size of the communication circuits is much smaller than the effective area limited by the power dissipation density. Thus, in any parallel computing application, there is an optimal ratio between the communication and the computation circuit area that maximizes the usage of available silicon real estate.