Abstract
Three-dimensional techniques are emerging to package many electronic chips in a single 3D assembly that can provide single chip like performance. Due to the inherent parallelism used in these packages, large I/O bandwidths are possible. A direct application of these techniques is the 3D DRAM stacks. 3D packaging allows for larger capacity memories to be built without incurring a significant increase in access times. Moreover, due to their dimensional compatibility, 3D memories and 3D packaged electronic processing systems may be naturally well suited to each other's needs. This paper explores the possibilities and attempts to outline means by which these devices can be interfaced advantageously.
| Original language | English (US) |
|---|---|
| Number of pages | 1 |
| Journal | Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS |
| Volume | 2 |
| State | Published - Dec 1 1995 |
| Externally published | Yes |
| Event | Proceedings of the 1995 8th Annual Meeting of the IEEE Lasers and Electro-Optics Society. Part 1 (of 2) - San Francisco, CA, USA Duration: Oct 30 1995 → Nov 2 1995 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering