Modular architecture for smart pixel switching networks

Fouad Kiamilev, Ashok V. Krishnamoorthy, Sadik C. Esener

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

Multistage interconnection networks based on the perfect shuffle topology are often suggested as candidates for large scale multiprocessor and broadband communication networks. The perfect shuffle interconnection requires global communication links that extend across the entire system and have a large number of wire crossovers. These constraints prohibit a scalable electronic implementation both within a VLSI chip and at the MCM or board levels1,2. This paper presents the architecture of a scalable optoelectronic hardware module for building multistage interconnection networks. To achieve a scalable implementation, the design uses free-space optical interconnects for global communication links and electronic VLSI technology for local communication links and switching elements (e.g. smart pixel approach). Our approach is to engineer a network with the desired functionality, cost and performance characteristics using generic hardware modules. In this paper, various applications are examined and their implementation using the proposed method is described.

Original languageEnglish (US)
Pages (from-to)129-140
Number of pages12
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume1849
DOIs
StatePublished - Jul 1 1993
Externally publishedYes
EventOptoelectronic Interconnects 1993 - Los Angeles, United States
Duration: Jan 17 1993Jan 22 1993

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

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