TY - GEN
T1 - High speed parallel multi-chip interconnection with free space optics
AU - Zheng, Xuezhe
AU - Marchand, Philippe J.
AU - Huang, Dawei
AU - Esener, Sadik C.
N1 - Publisher Copyright:
© 1999 IEEE.
PY - 1999
Y1 - 1999
N2 - In this paper, a high-speed parallel data communication scheme is proposed for multi-chip interconnections. We present the proof of concept and feasibility demonstration of a practical module packaging approach where free-space optical interconnects can be seamlessly integrated on electronic Multi-Chip Modules (MCM) for intra MCM interconnects. Our system level packaging architecture is based on a modified folded 4-f imaging system that has been implemented using only off-the-shelf optics, conventional electronic packaging, as well as passive alignment and assembly techniques to yield a potentially low cost manufacturable packaging solution. The prototype system, as built, supports 48 independent FSOI channels using eight separate laser and detector chips, where each chip consists of a 1D array of 12 devices. All chips are assembled on a single ceramic substrate together with three silicon chips. Parallel opto-electronic free space interconnections have been demonstrated with link speeds of up to 200 MHz per channel. The system is compact at only 10 cubic inches, and scalable as it can easily accommodate additional chips as well as two-dimensional opto-electronic device arrays for increased interconnection density.
AB - In this paper, a high-speed parallel data communication scheme is proposed for multi-chip interconnections. We present the proof of concept and feasibility demonstration of a practical module packaging approach where free-space optical interconnects can be seamlessly integrated on electronic Multi-Chip Modules (MCM) for intra MCM interconnects. Our system level packaging architecture is based on a modified folded 4-f imaging system that has been implemented using only off-the-shelf optics, conventional electronic packaging, as well as passive alignment and assembly techniques to yield a potentially low cost manufacturable packaging solution. The prototype system, as built, supports 48 independent FSOI channels using eight separate laser and detector chips, where each chip consists of a 1D array of 12 devices. All chips are assembled on a single ceramic substrate together with three silicon chips. Parallel opto-electronic free space interconnections have been demonstrated with link speeds of up to 200 MHz per channel. The system is compact at only 10 cubic inches, and scalable as it can easily accommodate additional chips as well as two-dimensional opto-electronic device arrays for increased interconnection density.
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U2 - 10.1109/PI.1999.806390
DO - 10.1109/PI.1999.806390
M3 - Conference contribution
AN - SCOPUS:0038156566
T3 - Proceedings - 6th International Conference on Parallel Interconnects, PI 1999
SP - 13
EP - 20
BT - Proceedings - 6th International Conference on Parallel Interconnects, PI 1999
A2 - Schenfeld, Eugen
A2 - Kostuk, Ray
A2 - Lund, Craig
A2 - Haney, Michael
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Conference on Parallel Interconnects, PI 1999
Y2 - 17 October 1999 through 19 October 1999
ER -