TY - JOUR
T1 - High-speed CMOS switch designs for free-space optoelectronic MIN's
AU - Kibar, Osman
AU - Marchand, Philippe J.
AU - Esener, Sadik C.
N1 - Funding Information:
Manuscript received October 15, 1995; revised November 15, 1997. This work was supported by DARPA under Contract F30601-93-C-0173. The authors are with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA. Publisher Item Identifier S 1063-8210(98)05969-1.
PY - 1998
Y1 - 1998
N2 - We present the theory, experimental results, and analytical modeling of high-speed complementary metal-oxide-semiconductor (CMOS) switches, with a two-dimensional (2-D) layout, suitable for the implementation of packet-switched free-space optoelectronic multistage interconnection networks (MIN's). These switches are fully connected, bidirectional, and scaleable. The design is based on the implementation of a half-switch, which is a two-to-one multiplexer, using a 2-D layout. It introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5 V being the third value for a 5 V power supply. Simulations show that for a 0.8-μm CMOS technology the switches can operate at speeds up to 250 Mb/s. Scaled-down versions of the switches have been successfully implemented in 2.0 μm CMOS. The analytical modeling of these switches show that large scale free-space optoelectronic MIN's using this concept could offer close to Terabit/sec throughput capabilities for very reasonable power and area figures. For example, a 4096 channel system could offer 256 Gb/s aggregate throughput for a total silicon area of about 18 cm2 and a total power consumption (optics plus electronics) of about 90 W.
AB - We present the theory, experimental results, and analytical modeling of high-speed complementary metal-oxide-semiconductor (CMOS) switches, with a two-dimensional (2-D) layout, suitable for the implementation of packet-switched free-space optoelectronic multistage interconnection networks (MIN's). These switches are fully connected, bidirectional, and scaleable. The design is based on the implementation of a half-switch, which is a two-to-one multiplexer, using a 2-D layout. It introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5 V being the third value for a 5 V power supply. Simulations show that for a 0.8-μm CMOS technology the switches can operate at speeds up to 250 Mb/s. Scaled-down versions of the switches have been successfully implemented in 2.0 μm CMOS. The analytical modeling of these switches show that large scale free-space optoelectronic MIN's using this concept could offer close to Terabit/sec throughput capabilities for very reasonable power and area figures. For example, a 4096 channel system could offer 256 Gb/s aggregate throughput for a total silicon area of about 18 cm2 and a total power consumption (optics plus electronics) of about 90 W.
KW - Analytical modeling of CMOS circuits
KW - Free-space optoelectronic interconnections
KW - Multistage interconnection networks
KW - Parallel systems
KW - Three-valued logic
KW - Two-dimensional layout
KW - VLSI switches
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U2 - 10.1109/92.711309
DO - 10.1109/92.711309
M3 - Article
AN - SCOPUS:0032167139
SN - 1063-8210
VL - 6
SP - 372
EP - 386
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 3
ER -