Free-space optics for 3D multi-chip environment

P. Marchand, Sadik Esener

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. We believe that, providing optoelectronic I/O to 3D chip stacks using VCSEL arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals provide the most efficient way to communicate between the stacks. By integrating these components with a set of packaging techniques ranging from silicon micro-bench to plastic molded lenses, we are presently engaged in demonstrating the practical superiority of this approach in terms of system speed, power and volume metrics. We address various aspects of this approach that are being explored within the 3D-OESP consortium.

Original languageEnglish (US)
Title of host publication2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages7-8
Number of pages2
ISBN (Electronic)0780359755, 9780780359758
DOIs
StatePublished - 2000
Externally publishedYes
EventSouthwest Symposium on Mixed-Signal Design, SSMSD 2000 - San Diego, United States
Duration: Feb 27 2000Feb 29 2000

Other

OtherSouthwest Symposium on Mixed-Signal Design, SSMSD 2000
CountryUnited States
CitySan Diego
Period2/27/002/29/00

Fingerprint

Space optics
Optoelectronic devices
Packaging
Plastic lenses
Microoptics
Optical receivers
Silicon
Surface emitting lasers
Hardware
Processing
Industry

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

Cite this

Marchand, P., & Esener, S. (2000). Free-space optics for 3D multi-chip environment. In 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000 (pp. 7-8). [836434] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SSMSD.2000.836434

Free-space optics for 3D multi-chip environment. / Marchand, P.; Esener, Sadik.

2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000. Institute of Electrical and Electronics Engineers Inc., 2000. p. 7-8 836434.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Marchand, P & Esener, S 2000, Free-space optics for 3D multi-chip environment. in 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000., 836434, Institute of Electrical and Electronics Engineers Inc., pp. 7-8, Southwest Symposium on Mixed-Signal Design, SSMSD 2000, San Diego, United States, 2/27/00. https://doi.org/10.1109/SSMSD.2000.836434
Marchand P, Esener S. Free-space optics for 3D multi-chip environment. In 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000. Institute of Electrical and Electronics Engineers Inc. 2000. p. 7-8. 836434 https://doi.org/10.1109/SSMSD.2000.836434
Marchand, P. ; Esener, Sadik. / Free-space optics for 3D multi-chip environment. 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000. Institute of Electrical and Electronics Engineers Inc., 2000. pp. 7-8
@inproceedings{accb5ffedc6e4b0ebdac44260ac155b5,
title = "Free-space optics for 3D multi-chip environment",
abstract = "The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. We believe that, providing optoelectronic I/O to 3D chip stacks using VCSEL arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals provide the most efficient way to communicate between the stacks. By integrating these components with a set of packaging techniques ranging from silicon micro-bench to plastic molded lenses, we are presently engaged in demonstrating the practical superiority of this approach in terms of system speed, power and volume metrics. We address various aspects of this approach that are being explored within the 3D-OESP consortium.",
author = "P. Marchand and Sadik Esener",
year = "2000",
doi = "10.1109/SSMSD.2000.836434",
language = "English (US)",
pages = "7--8",
booktitle = "2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Free-space optics for 3D multi-chip environment

AU - Marchand, P.

AU - Esener, Sadik

PY - 2000

Y1 - 2000

N2 - The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. We believe that, providing optoelectronic I/O to 3D chip stacks using VCSEL arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals provide the most efficient way to communicate between the stacks. By integrating these components with a set of packaging techniques ranging from silicon micro-bench to plastic molded lenses, we are presently engaged in demonstrating the practical superiority of this approach in terms of system speed, power and volume metrics. We address various aspects of this approach that are being explored within the 3D-OESP consortium.

AB - The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. We believe that, providing optoelectronic I/O to 3D chip stacks using VCSEL arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals provide the most efficient way to communicate between the stacks. By integrating these components with a set of packaging techniques ranging from silicon micro-bench to plastic molded lenses, we are presently engaged in demonstrating the practical superiority of this approach in terms of system speed, power and volume metrics. We address various aspects of this approach that are being explored within the 3D-OESP consortium.

UR - http://www.scopus.com/inward/record.url?scp=84962016185&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84962016185&partnerID=8YFLogxK

U2 - 10.1109/SSMSD.2000.836434

DO - 10.1109/SSMSD.2000.836434

M3 - Conference contribution

AN - SCOPUS:84962016185

SP - 7

EP - 8

BT - 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000

PB - Institute of Electrical and Electronics Engineers Inc.

ER -