TY - GEN
T1 - Free-space optics for 3D multi-chip environment
AU - Marchand, P.
AU - Esener, S.
N1 - Publisher Copyright:
© 2000 IEEE.
PY - 2000
Y1 - 2000
N2 - The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. We believe that, providing optoelectronic I/O to 3D chip stacks using VCSEL arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals provide the most efficient way to communicate between the stacks. By integrating these components with a set of packaging techniques ranging from silicon micro-bench to plastic molded lenses, we are presently engaged in demonstrating the practical superiority of this approach in terms of system speed, power and volume metrics. We address various aspects of this approach that are being explored within the 3D-OESP consortium.
AB - The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. We believe that, providing optoelectronic I/O to 3D chip stacks using VCSEL arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals provide the most efficient way to communicate between the stacks. By integrating these components with a set of packaging techniques ranging from silicon micro-bench to plastic molded lenses, we are presently engaged in demonstrating the practical superiority of this approach in terms of system speed, power and volume metrics. We address various aspects of this approach that are being explored within the 3D-OESP consortium.
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U2 - 10.1109/SSMSD.2000.836434
DO - 10.1109/SSMSD.2000.836434
M3 - Conference contribution
AN - SCOPUS:84962016185
T3 - 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000
SP - 7
EP - 8
BT - 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Southwest Symposium on Mixed-Signal Design, SSMSD 2000
Y2 - 27 February 2000 through 29 February 2000
ER -