Design trade-offs in optoelectronic parallel processing systems using smart-SLMs

D. T. Lu, V. H. Ozguz, P. J. Marchand, A. V. Krishnamoorthy, F. Kiamilev, R. Paturi, S. H. Lee, Sadik Esener

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Optoelectronic devices with free-space optical interconnections offer new possibilities in massively parallel processing. The trade-offs involved in system design and device selection for optoelectronic implementations are examined. System design trade-offs are approached from algorithmic and technological standpoints. From the algorithmic standpoint, new architectures based on expander graphs, that have been shown to provide low-contention fault-tolerant communication, are discussed. Optoelectronic systems which implement such random graphs can be folded to reduce the hardware cost or unfolded to increase bandwidth. They can also be partially folded by increasing the grain size or by reducing the randomness of the graph topology to reduce the complexity of the interconnection holograms. An optoelectronic and a VLSI implementation of a multistage interconnection network are compared from a technological standpoint. Physical design parameters, such as the chip size or the number of phase levels of the interconnection holograms, are related to the system design metrics such as bandwidth, volume, area and power. It is shown that the optoelectronic implementations have higher performance and are more cost-effective than VLSI implementations. These results are also used to provide general guidelines for device selection in the design of smart pixels/smart spatial light modulators based optoelectronic systems.

Original languageEnglish (US)
JournalOptical and Quantum Electronics
Volume24
Issue number4
DOIs
StatePublished - Apr 1992
Externally publishedYes

Fingerprint

Parallel processing systems
Optoelectronic devices
systems engineering
very large scale integration
Systems analysis
Holograms
bandwidth
costs
light modulators
optoelectronic devices
Bandwidth
hardware
Optical interconnects
topology
grain size
communication
pixels
chips
Costs
Pixels

ASJC Scopus subject areas

  • Atomic and Molecular Physics, and Optics
  • Electrical and Electronic Engineering

Cite this

Lu, D. T., Ozguz, V. H., Marchand, P. J., Krishnamoorthy, A. V., Kiamilev, F., Paturi, R., ... Esener, S. (1992). Design trade-offs in optoelectronic parallel processing systems using smart-SLMs. Optical and Quantum Electronics, 24(4). https://doi.org/10.1007/BF00619508

Design trade-offs in optoelectronic parallel processing systems using smart-SLMs. / Lu, D. T.; Ozguz, V. H.; Marchand, P. J.; Krishnamoorthy, A. V.; Kiamilev, F.; Paturi, R.; Lee, S. H.; Esener, Sadik.

In: Optical and Quantum Electronics, Vol. 24, No. 4, 04.1992.

Research output: Contribution to journalArticle

Lu, DT, Ozguz, VH, Marchand, PJ, Krishnamoorthy, AV, Kiamilev, F, Paturi, R, Lee, SH & Esener, S 1992, 'Design trade-offs in optoelectronic parallel processing systems using smart-SLMs', Optical and Quantum Electronics, vol. 24, no. 4. https://doi.org/10.1007/BF00619508
Lu DT, Ozguz VH, Marchand PJ, Krishnamoorthy AV, Kiamilev F, Paturi R et al. Design trade-offs in optoelectronic parallel processing systems using smart-SLMs. Optical and Quantum Electronics. 1992 Apr;24(4). https://doi.org/10.1007/BF00619508
Lu, D. T. ; Ozguz, V. H. ; Marchand, P. J. ; Krishnamoorthy, A. V. ; Kiamilev, F. ; Paturi, R. ; Lee, S. H. ; Esener, Sadik. / Design trade-offs in optoelectronic parallel processing systems using smart-SLMs. In: Optical and Quantum Electronics. 1992 ; Vol. 24, No. 4.
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