Design of interconnection networks for programmable optoelectronic multiprocessor technology

Programmable optoelectronic multiprocessor (POEM) architecture is based on wafer-scale integration of optoelectronic processing elements (PEs) and reconfigurable free-space interconnects. Calculations and prototype development show that it is possible to have over 100K simple one-bit PEs per wafer. Since an important architectural feature of a parallel computer is its interconnection network linking the processing elements, the authors evaluate interconnection networks based on POEM technology. They consider various multistage interconnection network topologies such as the perfect shuffle, butterfly, banyan and data manipulator and evaluate how well they map onto the POEM technology. They determine the effects of varying the grain size of the router switches, network control, fault tolerance and interconnection topology on network performance and compare the performance of POEM networks with VLSI-based interconnection networks and the proposed optical digital switch architecture based on symbolic substitution.