Design of a scalable opto-electronic neural system using free-space optical interconnects

A. V. Krishnamoorthy, G. Yayla, Sadik Esener

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The authors describe a three-dimensional opto-electronic neural system that uses a hybrid silicon VLSI-based opto-electronic integrated circuit (OEIC) technology to implement the neurons and their associated synapses and fixed, free-space optical diffractive elements to interconnect the neurons. The architecture provides full connectivity between neurons, flexible functionality of neurons and synapses, accurate electronic fan-in, and biologically inspired dendritic-type fan-in processing. The system requirements for neural network implementations are addressed. The architecture is described, and the technological feasibility of the system is discussed. Optimal data encoding methods are proposed. Low-area circuit designs with learning capabilities that achieve high linear dynamic range are presented.

Original languageEnglish (US)
Title of host publicationProceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks
Editors Anon
PublisherPubl by IEEE
Pages527-534
Number of pages8
ISBN (Print)0780301641
StatePublished - 1991
Externally publishedYes
EventInternational Joint Conference on Neural Networks - IJCNN-91-Seattle - Seattle, WA, USA
Duration: Jul 8 1991Jul 12 1991

Other

OtherInternational Joint Conference on Neural Networks - IJCNN-91-Seattle
CitySeattle, WA, USA
Period7/8/917/12/91

Fingerprint

Optical interconnects
Neurons
Diffractive optical elements
Integrated optoelectronics
Neural networks
Silicon
Networks (circuits)
Processing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Krishnamoorthy, A. V., Yayla, G., & Esener, S. (1991). Design of a scalable opto-electronic neural system using free-space optical interconnects. In Anon (Ed.), Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks (pp. 527-534). Publ by IEEE.

Design of a scalable opto-electronic neural system using free-space optical interconnects. / Krishnamoorthy, A. V.; Yayla, G.; Esener, Sadik.

Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks. ed. / Anon. Publ by IEEE, 1991. p. 527-534.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Krishnamoorthy, AV, Yayla, G & Esener, S 1991, Design of a scalable opto-electronic neural system using free-space optical interconnects. in Anon (ed.), Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks. Publ by IEEE, pp. 527-534, International Joint Conference on Neural Networks - IJCNN-91-Seattle, Seattle, WA, USA, 7/8/91.
Krishnamoorthy AV, Yayla G, Esener S. Design of a scalable opto-electronic neural system using free-space optical interconnects. In Anon, editor, Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks. Publ by IEEE. 1991. p. 527-534
Krishnamoorthy, A. V. ; Yayla, G. ; Esener, Sadik. / Design of a scalable opto-electronic neural system using free-space optical interconnects. Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks. editor / Anon. Publ by IEEE, 1991. pp. 527-534
@inproceedings{ec8c1652bd954dceaada89bbed04a9bd,
title = "Design of a scalable opto-electronic neural system using free-space optical interconnects",
abstract = "The authors describe a three-dimensional opto-electronic neural system that uses a hybrid silicon VLSI-based opto-electronic integrated circuit (OEIC) technology to implement the neurons and their associated synapses and fixed, free-space optical diffractive elements to interconnect the neurons. The architecture provides full connectivity between neurons, flexible functionality of neurons and synapses, accurate electronic fan-in, and biologically inspired dendritic-type fan-in processing. The system requirements for neural network implementations are addressed. The architecture is described, and the technological feasibility of the system is discussed. Optimal data encoding methods are proposed. Low-area circuit designs with learning capabilities that achieve high linear dynamic range are presented.",
author = "Krishnamoorthy, {A. V.} and G. Yayla and Sadik Esener",
year = "1991",
language = "English (US)",
isbn = "0780301641",
pages = "527--534",
editor = "Anon",
booktitle = "Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - Design of a scalable opto-electronic neural system using free-space optical interconnects

AU - Krishnamoorthy, A. V.

AU - Yayla, G.

AU - Esener, Sadik

PY - 1991

Y1 - 1991

N2 - The authors describe a three-dimensional opto-electronic neural system that uses a hybrid silicon VLSI-based opto-electronic integrated circuit (OEIC) technology to implement the neurons and their associated synapses and fixed, free-space optical diffractive elements to interconnect the neurons. The architecture provides full connectivity between neurons, flexible functionality of neurons and synapses, accurate electronic fan-in, and biologically inspired dendritic-type fan-in processing. The system requirements for neural network implementations are addressed. The architecture is described, and the technological feasibility of the system is discussed. Optimal data encoding methods are proposed. Low-area circuit designs with learning capabilities that achieve high linear dynamic range are presented.

AB - The authors describe a three-dimensional opto-electronic neural system that uses a hybrid silicon VLSI-based opto-electronic integrated circuit (OEIC) technology to implement the neurons and their associated synapses and fixed, free-space optical diffractive elements to interconnect the neurons. The architecture provides full connectivity between neurons, flexible functionality of neurons and synapses, accurate electronic fan-in, and biologically inspired dendritic-type fan-in processing. The system requirements for neural network implementations are addressed. The architecture is described, and the technological feasibility of the system is discussed. Optimal data encoding methods are proposed. Low-area circuit designs with learning capabilities that achieve high linear dynamic range are presented.

UR - http://www.scopus.com/inward/record.url?scp=0026376523&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026376523&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0026376523

SN - 0780301641

SP - 527

EP - 534

BT - Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks

A2 - Anon, null

PB - Publ by IEEE

ER -